The fabrication sequence of integrated circuits often includes several patterning processes. The patterning processes may define a layer of conductors, such as a patterned metal or polysilicon layer, or may define isolation structures, such as trenches. In many cases the trenches are filled with an insulating, or dielectric, material. This insulating material can serve several functions. For example, in some applications the material serves to both electrically isolate one region of the IC from another, and electrically passivate the surface of the trench. The material also typically provides a base for the next layer of the semiconductor to be built upon.
After patterning a substrate, the patterned material is not flat. The topology of the pattern can interfere with or degrade subsequent wafer processing. It is often desirable to create a flat surface over the patterned material. Several methods have been developed to create such a flat, or “planarized”, surface. Examples include depositing a conformal layer of material of sufficient thickness and polishing the wafer to obtain a flat surface, depositing a conformal layer of material of sufficient thickness and etching the layer back to form a planarized surface, and forming a layer of relatively low-melting point material, such as doped silicon oxide, and then heating the wafer sufficiently to cause the doped silicon oxide to melt and flow as a liquid, resulting in a flat surface upon cooling. Each process has attributes that make that process desirable for a specific application.
As semiconductor design has advanced, the feature size of the semiconductor devices has dramatically decreased. Many circuits now have features, such as traces or trenches less than a micron across. While the reduction in feature size has allowed higher device density, more chips per wafer, more complex circuits, lower operating power consumption and lower cost among other benefits, the smaller geometries have also given rise to new problems, or have resurrected problems that were once solved for larger geometries.
An example of the type of manufacturing challenge presented by sub-micron devices is the ability to completely fill a narrow trench in a void-free manner. To fill a trench with silicon oxide, a layer of silicon oxide is first deposited on the patterned substrate. The silicon oxide layer typically covers the field, as well as walls and bottom of the trench. If the trench is wide and shallow, it is relatively easy to completely fill the trench. As the trench gets narrower and the aspect ratio (the ratio of the trench height to the trench width) increases, it becomes more likely that the opening of the trench will “pinch off”.
Pinching off a trench may trap a void within the trench. FIG. 1 shows such a void 4 formed in the dielectric material 2 that fills trench 1. These voids commonly occur in gapfill depositions where dielectric materials are rapidly deposited in high aspect ratio trenches. Void 4 creates inhomogeneities in the dielectric strength of the gapfill that can adversely affect the operation of a semiconductor device.
One approach to forming fewer voids is to slow down the dielectric deposition rate. Slower deposition rates facilitate a more conformal deposition of the dielectric material on the trench surfaces, which reduces excess buildup of dielectric materials on the top corners of the trench that can result in pinching off. As a result, trenches are more evenly filled from the bottom up. However, lowering the deposition rate of the dielectric material also reduces process efficiency by increasing the total dielectric deposition time. The slower dielectric deposition rates not only increase the time for filling trench 1, but also the bulk dielectric layer 3 on top of trench 1.
Another challenge encountered in gap-fill processes is the formation of weak seams at the interface of the dielectric material with a trench surface, as well as between surfaces of the dielectric materials itself. Weak seams can form when the deposited dielectric materials adhere weakly, or not at all, to the inside surfaces of a trench. Subsequent process steps (e.g., annealing) can detach the dielectric material from the trench surface and create a fissure in the gap-filled trench. Weak seams can also be formed between dielectric surfaces as illustrated in FIG. 2A, which shows a weak seam 9 in the middle of trench 5 that has been formed at the intersection of opposite faces of silicon oxide material 6 growing outward from opposite sidewalls (7a and 7b) of trench 5.
The dielectric material along seam 9 has a lower density and higher porosity than other portions of the dielectric material 6, which can cause an enhanced rate of etching along the seam 9. FIG. 2B illustrates how unwanted dishing 8 can develop along seam 4 when the dielectric material 6 is exposed to an etchant (e.g., HF) during processes such as chemical-mechanical polishing (CMP) and post-CMP cleaning. Like voids, weak seams create inhomogeneities in the dielectric strength of the gapfill that can adversely affect the operation of a semiconductor device.
In some circumstances, voids and weak seams in dielectric trench fills may be filled in or “healed” using a reflow process. For example, some doped silicon oxide dielectric materials experience viscous flow at elevated temperatures, permitting the reduction of voids and weak seams with high-temperature reflow processes. However, as the trench becomes narrower, it becomes more likely that the void will not be filled during these reflow process. In addition, reflow processes are not practical in many applications where high melting point dielectrics, such as undoped silicon oxide, are used for the gapfill. Thus, there remains a need for new systems and methods to reduce or eliminate voids and weak seams in dielectric gapfills.